BIOS Tuning for Telco Workloads on Dell PowerEdge XR8620t

Software tuning — kernel parameters, CPU isolation, huge pages — can only go so far. The foundation of a real-time platform is the BIOS configuration. A badly tuned BIOS will introduce latency spikes that no amount of kernel configuration can fix. This post documents the production BIOS settings for the Dell PowerEdge XR8620t nodes in the EIB-Customer deployment.

Hardware Platform: Dell PowerEdge XR8620t

The XR8620t is Dell's telecom-grade edge server — purpose-built for 5G RAN deployments at the network edge:

Form factor: Rugged chassis for edge/telco environments
Target use cases: 5G DU, CU, UPF, vRAN
Certifications: NEBS Level 3 (Network Equipment Building System)
Power: DC power support for telco rack installations
Cooling: Enhanced thermal management for non-data-centre environments

Node	Service Tag	IP Address	Role
Node 1	13V6554	192.168.41.3	Server + Worker
Node 2	97D5C24	192.168.41.4	Worker

TelcoOptimizedProfile: The Starting Point

Dell provides a pre-configured workload profile specifically for telecommunications. Selecting TelcoOptimizedProfile in the BIOS sets a baseline of telco-appropriate defaults:

{
  "WorkloadProfile": "TelcoOptimizedProfile",
  "SysProfile": "PerfOptimized",
  "ProcPwrPerf": "MaxPerf"
}

What this profile enables by default:

CPU frequency locked to maximum — no dynamic frequency scaling
C-states disabled — no CPU idle power states
P-states optimised for performance over power efficiency
Memory frequency set to maximum rated speed
PCIe ASPM (Active State Power Management) disabled
Prefetchers tuned for telco packet processing patterns
Interrupt coalescing optimised for low latency

Why this matters: C-state transitions can take 10–100μs as the CPU wakes from a power-saving state. For a 5G DU with a 125μs subframe processing deadline, a single C-state transition can consume most of the timing budget.

Critical BIOS Settings

Processor Configuration

Setting	Value	Reason
C1E State	Disabled	Prevent CPU idle latency
C States	Disabled	No power-saving idle states
Turbo Boost	Enabled	Max single-core frequency for latency-critical paths
Hyper-Threading	Enabled	Doubles logical core count (64 → 128 for general use)
Virtualization (VT-x)	Enabled	Required for container runtime
VT-d (IOMMU)	Enabled	Required for SR-IOV and DPDK vfio-pci

IOMMU must be enabled in BIOS and the kernel (intel_iommu=on iommu=pt in cmdline). Without it, vfio-pci driver binding for DPDK SMC's will fail silently.

Memory Configuration

Setting	Value	Reason
Memory Speed	Maximum rated	Reduce DRAM latency for packet buffers
Memory Operating Mode	Optimizer Mode	Maximise bandwidth over RAS features
NUMA	Enabled	Expose NUMA topology to OS for policy enforcement
Memory Patrol Scrub	Disabled	Patrol scrub causes periodic memory bus contention

PCIe / SR-IOV Configuration

Setting	Value	Reason
SR-IOV Global Enable	Enabled	Required to create SMC's on Intel E810 NIC
PCIe ASPM	Disabled	PCIe link power management adds latency on wake
PCIe Max Payload	256B or 512B	Larger payloads improve DMA throughput

Power Management

Setting	Value	Reason
System Profile	Performance Optimised	No power capping
CPU Power Management	Maximum Performance	OS cannot scale CPU frequency
Power Cap Policy	Disabled	Power limits cause frequency throttling
Energy Efficient Turbo	Disabled	Prevents turbo frequency reduction under load

Hardware Prefetcher Tuning

Hardware prefetchers speculatively load cache lines from memory ahead of program access. For sequential workloads (general compute) they help. For telco packet processing — where access patterns are irregular — they generate unnecessary memory bus traffic and can evict live data from cache.

The TelcoOptimizedProfile disables or reduces prefetcher aggressiveness:

DCU Streamer Prefetcher: Disabled — reduces cache pollution from prefetched lines that are never used
DCU IP Prefetcher: Disabled — IP-based prediction doesn't match DPDK poll loop patterns
Adjacent Cache Line Prefetch: Disabled — prevents double-cache-line fetches on random access

Prefetcher settings have a significant impact on DPDK PMD performance. Benchmarking your specific workload with prefetchers enabled vs disabled is recommended — the optimal setting depends on the NIC and application's access pattern.

NUMA Topology

The Intel Xeon processors in the XR8620t expose a two-NUMA-node topology. Correct BIOS NUMA configuration is essential for the kernel's topology policy to work:

NUMA must be enabled in BIOS (not interleaved mode)
OS must see the NUMA topology via ACPI SLIT/SRAT tables
Verify: numactl --hardware should show 2 nodes with local and cross-node latencies

# Verify NUMA visibility
numactl --hardware
# available: 2 nodes (0-1)
# node 0 cpus: 0 1 2 ... 31
# node 1 cpus: 32 33 34 ... 63
# node distances:
# node   0   1
#   0:  10  21
#   1:  21  10

Validation Checklist

After applying BIOS settings and booting the OS:

# Verify no C-states active
cat /sys/devices/system/cpu/cpu0/cpuidle/state*/name
# Should show: POLL C1 (or just POLL if C-states fully disabled)

# Verify CPU governor
cat /sys/devices/system/cpu/cpu*/cpufreq/scaling_governor | sort -u
# Expected: performance

# Verify SR-IOV capability
cat /sys/bus/pci/devices/*/sriov_totalvfs | grep -v "^0$"
# Expected: 64 (or similar) for the E810 NIC

# Verify IOMMU active
dmesg | grep -i iommu
# Expected: DMAR: IOMMU enabled

Getting the BIOS right is a prerequisite for everything else. The kernel's CPU isolation, the DPDK performance, the SR-IOV SMC creation — all of it depends on the hardware being configured to expose the right capabilities and not interfere with deterministic execution.